This invention relates to filter circuits and, more particularly, to low-pass filter circuits of the type suitable for use in a phase locked loop (PLL).
PLL's find utility in numerous applications where it is desired to generate signals having controllable frequency characteristics. For example, in television tuning systems of the electronic type it is typically necessary to develop tuning voltages for application to one or more tuning elements in order to establish a local oscillator frequency (LOF) corresponding to a selected television channel. For viewer convenience the LOF corresponding to the selected channel should be acquired or "locked onto" as quickly as possible. For this purpose, it has been found useful to initially develop a tuning voltage for application to the tuning elements which cause them to rapidly approach the desired LOF and to subsequently stabilize tuning under the influence of a PLL. Following tuning stabilization, system tuning may be maintained by the PLL or, alternatively, turned over to an automatic frequency control system. In either event, the use of the PLL to facilitate system tuning is an extremely useful technique.
Conventional phase locked loops include a voltage controlled oscillator (VCO) for developing an output signal having a frequency f.sub.O which is fed back to one input of a phase detector or comparator, the other input of the phase comparator being supplied with a reference signal having a frequency f.sub.ref from a crystal reference or the like. Based on the frequency and phase deviation between the oscillator output signal and the reference signal, the phase comparator develops an error signal, usually a series of pulses, which is applied through a low-pass filter to the VCO in a corrective direction to cause the frequency f.sub.O of its output to stabilize at a value equivalent to the frequency f.sub.ref of the reference signal.
It is also known in the prior art to utilize a programable divider or the like in the feedback loop between the oscillator and the phase comparator to provide for an increased range of output signals. That is, since the reference signal has a constant frequency, the VCO output can be made to equal any integral multiple of the reference signal frequency by setting the division factor of the divider to a particular value. Thus, the frequency f.sub.O of the oscillator output can be made to equal Nf.sub.ref where N is the division factor of the feedback divider.
It is further known that the fundamental characteristics of a PLL are controlled primarily by the loop's lowpass filter. For example, to achieve a reasonably low capture time, i.e., a high acquisition speed, it is preferable to utilize a low capacitance network capable of rapidly charging or discharging to a desired tuning voltage for controlling the oscillator. However, the use of a low capacitance charging and discharging network results in increased loop bandwidth which tends to compromise reference signal sideband suppression. In a television system, the failure to adequately suppress reference signal sidebands from being applied through the filter to the VCO may result in serious degradation of the displayed picture.
In order to accomodate the conflicting requirements for high acquisition speed and good reference signal sideband suppression it has heretofore been necessary to make certain design trade-offs. That is, for example, by somewhat reducing the acquisition speed, an acceptable level of reference signal sideband suppression my be achieved. It is also known to use a reference signal having a relatively high frequency to facilitate reference signal sideband suppression by the low-pass filter without unduly compromising acquisition speed. Unfortunately, the use of a high frequency reference signal necessitates the use of relatively expensive, high-speed semiconductor technology to perform, for example, counting operations, and, even so, acquisition speed is frequently compromised to an unacceptable degree.